FIELD OF THE INVENTION
The invention relates to an integrated memory in which two items of data which are sequentially fed to the memory can be fed in different assignments in each case to one of two groups of memory cells.
Memory devices of this type include the type known as DDR-SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories), in which data are read in or out both with the rising edge and with the falling edge of an external clock signal. They contain a first group of memory cells, to which even column addresses are assigned, and a second cell group, to which odd column addresses are assigned. Depending on whether a start address fed to the memory is even or odd, the datum transferred with the rising edge of the external clock signal must be assigned to an even or odd column address, that is to say be stored either in the first or in the second cell group. A second datum received with a subsequent negative clock edge is then fed to the respective other cell group. During read-out from a DDR-SDRAM, two items of data are simultaneously read from the two cell groups. In this case, the order of these items of data upon being output from the memory again depends on whether the start address applied to the memory in the event of read-out is even or odd.
The information as to whether the start address that is present is an even or odd address is taken from the least significant bit (LSB) of the start address. A corresponding control signal for the memory is derived from this address bit.
To date, it has been customary for corresponding input circuits, serving for assigning the successively arriving data to the different cell groups, to be provided directly at the respective data connection. It has also been customary for output circuits, which output the data read simultaneously from the two cell groups in the event of a read access to the memory in the correct order, to be provided directly at the respective data connection.
The control signal derived from the least significant bit of the start address has to be fed both to the input circuit and to the output circuit. Depending on where the control signal is generated, the latter has to be driven via the entire chip in the worst-case scenario, in particular when the data connections are provided at the edge of the memory component. This results in a not inconsiderable propagation delay of the control signal, since the line lengths can be up to several millimeters. This propagation delay limits the maximum operating speed of the memory since, in the event of a write access, the data can be fed to the cell groups only after evaluation of the control signal by the input circuit provided at the data connection. This propagation delay of the control signal is less critical in the event of a read access since the data that are read out, in SDRAMs, are buffer-stored for one or more clock periods in a FIFO store (First IN, First OUT), before being output from the memory. This means that there is enough time available for the decision concerning the order in which the data read from the cell groups are to be output.